1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to an output pad circuit.
2. Background of the Related Art
As shown in FIG. 1, a related art output pad circuit includes an inverter IN1 for inverting an input data signal Din, and a CMOS inverter IN2 receiving an output of the inverter IN1. The inverter IN2 includes a PMOS transistor P1 and an NMOS transistor N1 coupled in series between a supply voltage Vcc and a ground voltage Vss. The gates of the NMOS transistor N1 and the PMOS transistor P1 are commonly coupled and receive the output of inverter IN1. An output pad circuit as shown in FIG. 2 is identical in composition to that of FIG. 1, except for the sizes of transistors P1, P2, N1, N2, i.e., the Beta ratios thereof.
The operation of the related art output pad circuit will now be described with reference to the accompanying drawings. First, when the input data signal Din is at a high level, the output value of the inverter IN1 becomes a low level, and the PMOS transistor P1 in the CMOS inverter IN2 is turned on in accordance with the output value of the inverter IN1. Accordingly, a high level data signal Dout is outputted through an output terminal.
When the input data signal Din is at a low level, the NMOS transistor N1 In the CMOS inverter IN2 is turned on in accordance with a high level output signal of the inverter IN1. Accordingly, a low level data signal Dout is outputted through the output terminal. The operation of the output pad circuit as shown in FIG. 2 is identical to that of FIG. 1.
Thus, the output pad circuits of FIGS. 1 and 2 function identically but are differentiated by respective sizes of the transistors P1, P2, N1, N2. Thus a respective size of an output driving current is different in accordance with the size of the respective transistors. Namely, the respective driving output currents of the inverters IN2, IN3 are different because of the sizes of the transistors P1, P2, N1, N2.
In comparing the inverter IN2 of the output pad circuit in FIG. 1 and the inverter IN3 of the output pad circuit in FIG. 2, PMOS transistor P2 and NMOS transistor N2 in inverter IN3 are respectively twice the respective size of PMOS transistor P1 and NMOS transistor N1 in inverter IN2. That is, the transistors are identical in length, but the transistors P2, N2 in the inverter IN3 are twice as the large as transistors P1, N1 in the inverter IN2 in width.
In such output pad circuits, the size of the output driving current is determined in accordance with that of the output transistors so that respective output pad circuits generate a proper output driving current value. The size of the output driving current of an output pad current is determined during a chip design by an external application connected to the corresponding output pad circuit.
That is, when the load on an output pad circuit is large, there is applied an output pad circuit having a correspondingly large output driving current. However, when a load on an output pad circuit is not large, the output pad circuit employs a correspondingly lesser output driving current.
In the related art output pad circuit, when the size of the output driving current of an output pad circuit does not match with an external load, an increased operation time for an external circuit or an increased peak current value during a level transition can occur. Namely, when the size of the output driving current in an output pad circuit is small compared to an external load, it takes more time for a voltage level to the external load to be assumed. To decrease the transition time, an external buffer circuit is required, or the preset output pad circuit in a chip can be replaced by an output pad circuit having a larger output driving current.
When the size of the output driving current in the output pad circuit is larger than an external load, a peak current value at a transition level of the output pad circuit becomes large enough to generate ground bouncing. As a result, an input/output ground fluctuates so that marginal driving voltages V.sub.iL, V.sub.iH in the output pad circuit can vary, which leads to an erroneous operation in the chip.